A Standalone Burst-Mode Receiver With Clock and Data Recovery, Clock Phase Alignment, and RS(255, 239) Codes for SAC-OCDMA Applications

Performance analysis of burst-mode receivers with clock phase alignment and forward error correction for GPON

We experimentally demonstrate the performance analysis of burst-mode receivers (BMRx) in a 622 Mb/s 20-km gigabit-capable passive optical network (GPON) uplink. Our receiver features automatic phase acquisition using a clock phase aligner (CPA), and forward-error correction using (255, 239) Reed-Solomon (RS) codes. The BMRx provides instantaneous (0 preamble bit) phase acquisition and a packet-...

A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling

Design of High-speed Burst Mode Clock and Data Recovery IC for Passive Optical Network

Design of a high bit rate burst mode clock and data recovery (BMCDR) circuit for gigabit passive optical networks (GPON) is described. A top-down design flow is established and some of the key issues related to the behavioural level modeling are addressed in consideration for the complexity of the BMCDR integrated circuit (IC). Precise implementation of Simulink behavioural model accounting for...

A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation

In this letter, a 1.25-Gb/s 0.18-μm CMOS half-rate burstmode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock...

High Speed Delay-Locked Loop for Multiple Clock Phase Generation

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...